3 nm process node: what it is, how it works and what it does

Definition

The 3 nm process node is a commercial and technical designation identifying a stage in the scaling of semiconductor fabrication processes. The figure «3 nm» refers to the etching fineness (finesse de gravure), i.e. the characteristic resolution of the pattern transferred onto the substrate during the lithography and etching phases of the integrated circuit.

It is important to note that the nanometre value does not correspond to the channel length of a specific transistor nor to the distance between two adjacent structures; it is a generation label that groups a set of dimensional parameters, transistor densities, and cell architectures.

Principles and operation

Node scaling is based on the progressive reduction of critical process dimensions. In practice, a 3 nm node implies:

• A lithography and etching resolution on the order of 3 nm, enabling the definition of structures smaller than those in previous nodes (5 nm, 7 nm, etc.).
• A higher transistor density per square millimetre of silicon, translating into more functionality in the same area or a more compact die.
• The adoption of advanced transistor architectures (e.g. gate-all-around or nanowire transistors) to maintain electrostatic control at such reduced scales.

The etching fineness referenced in technical documentation is the parameter that gives the node its name: it expresses the minimum pattern fineness that the process can reproducibly achieve.

Applications

Circuits fabricated at the 3 nm node are primarily intended for:

• High-performance processors (desktop, laptop, and server CPUs).
• Graphics processing units (GPUs) and artificial-intelligence accelerators.
• System-on-chip (SoC) designs for high-end mobile devices.

The choice of this node responds to the need to maximise performance per watt and functional density in products where energy consumption and die size are critical constraints.

Scope and limitations

The 3 nm node represents a frontier at which classical scaling laws (Dennard scaling) no longer apply linearly. Among the inherent limitations at this scale are:

• Increased complexity and cost of lithography equipment (multi-patterning EUV).
• Greater manufacturing variability and more demanding yield requirements.
• The need for new transistor architectures and materials to compensate for the degradation of electrostatic control.

Furthermore, the «3 nm» label is not a universal standard: different manufacturers may use the same designation for processes with different dimensional parameters and cell architectures, so the figure must be interpreted as a relative generation indicator rather than an absolute, cross-vendor comparable measurement.

Interpretation in a product

When a processor or SoC datasheet states a 3 nm node (e.g. «finesse de gravure 3 nm»), the reader should understand that:

1. The device was fabricated with a process whose etching resolution sits in the 3 nm range.
2. A significantly higher transistor density than 5 nm or 7 nm nodes is expected.
3. The figure alone does not guarantee specific performance or power figures; these also depend on the microarchitecture, clock frequency, and thermal management of the final product.

The presence of this specification in product documentation is therefore a process-generation indicator, useful for situating the device in the scaling context, but insufficient by itself to predict real-world behaviour.

Available evidence

The information gathered for this entry is based on a technical reference identifying the etching fineness as 3 nm in the context of a specific processor, published in a technology-outreach medium. The source authority is moderate and the confidence assigned to the datum is 0.88.

«Finesse de gravure 3 nm» — technical reference associated with a processor (claim 919).

It is recommended to complement this entry with the device manufacturer's official documentation to obtain exact dimensional parameters, the transistor architecture employed, and certified performance metrics.